Field programmable devices, especially field programmable gate arrays, are often used by product designers for implementing the desired logic when prototyping a system, and sometimes for a production system. Their use involves combining digital logic gates to provide certain digital functions by the device. The logic may be completely created by the designer using logic descriptive codings, such as the well-known Verilog, RTL, and such. While such is needed for custom logic and the interconnect between functional blocks, designers often times purchase pre-designed logical blocks from third party vendors, reusing the vendors' intellectual property (“IP”). This is less expensive and more faithful since the blocks are well simulated and tested by the provider, making development of the final combined product faster. For example, one may buy a logical block for serial communication, buffer management, floating point calculating and such rather than “inventing” them from scratch.
Vendors of logical blocks are motivated to allow potential customers to try a logical block to verify operation, but are concerned that a designer might download the logical block, program it into a field programmable device, and thereby be able to replicate the device, including the proprietary logic, for free.
To date, the generally accepted solution to this problem has been the use of legal evaluation agreements between the vendor and prospective purchaser which limit the use of the logic to a short period of time and expressly prohibit its use in production products. Such legal solutions inhibit effective selling and marketing of third party logic blocks using modern techniques such as those used by other types of products on the internet.
Some IP vendors have implemented crude solutions by placing clock counters within their proprietary logic. The counters shut off a clock signal when the counter saturates (or, “counts out”), thereby making the chip unusable. The problems with this approach are threefold. First, the fact that the logic is a simple standard counter and tied to the clock makes it easy to detect and be disconnected by a skilled engineer, thereby defeating the protection mechanism. Second, such solutions are not cognizant of the fact that many logic blocks are likely to be placed into the same system to create interoperability, and therefore one block may arbitrarily shut off portions of the chip before other sections of have run long enough to show interoperability, making the total design difficult or impossible to verify. Third, it is a common practice to circumvent clock based systems simply by periodically resetting the system before the counters saturate.
What is needed for today's complex system designs to enable more effective selling techniques is a means of limiting the use of proprietary logic blocks within a functioning system that limits the functionality of the logic so as to make it unusable in a production environment while enabling its functionality and interoperability to be fully tested.